Data is commonly transferred between mesochronous domains where the phase relationship between the synchronizing clocks of the two domains is arbitrary. This situation is illustrated in FIG. 1. The sending and receiving blocks (e.g., logic/data processing blocks) are said to be mesochronous if their synchronizing clocks have the same frequency but have an arbitrary phase relationship. This is typically the case if both clocks are generated from the same source such as an on-chip phase-locked loop (PLL).
The elements that actually transfer data are typically flip-flops, also known as registers. When data is transferred between two registers operating with the same synchronizing clock, it is fairly simple to comply with the set-up-and-hold time requirement for latching in data. This is due to the fact that data and clock propagation delays are typically known apriori and it is possible to compensate for these delays. On the other hand, when data is transferred between two mesochronous blocks as in FIG. 1, it is not possible to assume that the set-up-and-hold time requirement is satisfied. If the receiving block latches in the data without proper timing, error-free operation cannot be guaranteed.
In order to guarantee error-free data propagation, the incoming data must be transferred or “shifted” from the sending clock phase to the receiving clock phase. This point is illustrated in FIG. 2, wherein the synchronizing clock for the sending block is referred to as Pclk, and the synchronizing clock of the receiving block is referred to as Txclk. FIG. 2 shows a stream of random data, DataIn, which is synchronous with Pclk and is provided at the sending block output. On the other hand, DataIn has an arbitrary phase relationship to Txclk. This arbitrary phase relationship can result in bit errors as the data crosses the clock domain boundary between the sending and receiving blocks.
It is therefore desirable to provide for error-free data transfer across a clock domain boundary between first and second mesochronous clock domains.